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document number: TXC-02050C-mb ed. 1, may 2002 mrt device 6-, 8-, 34- mbit/s line interface TXC-02050C +5v equalization and rate los/loc ais control control 6-, 8-, 34- mbit/s line interface mrt operating rate reference frequency 6, 8, 34 mbit/s transmit bipolar data 6, 8, 34 mbit/s receive error rate clock reference bipolar data 10 -6 error rate indication line side terminal side TXC-02050C clock & data clock & data nrz or p, n r a i l the transwitch multi-rate receive/transmit (mrt) line interface is a cmos vlsi device that provides the functions needed for terminating two itu-t line rates, 8448 and 34368 kbit/s, or a 6312 kbit/s rate which is specified in the japanese ntt technical reference for high speed digital leased circuits. for 8448 and 34368 kbit/s operation, the mrt provides a selectable hdb3 codec. the mrt is equipped with a receive equalizer circuit and agc. the mrt also provides a rail or nrz interface, hdb3 error rate monitor, alarm detection, and ais generators. testing capability is provided by transmit and receive loopbacks. ? 6312/8448/34368 kbit/s line interface agc and equalizer line quality monitor (10 -6 error rate threshold) receive loss of signal and transmit loss of clock alarms selectable hdb3 encoder/decoder two loopbacks: - receive to transmit - transmit to receive receive and transmit ais generators rail or nrz terminal side i/o coding violation monitor meets itu-t rec. g.703 pulse masks meets itu-t rec. g.823 and jt-670,3 jitter requirements 44-pin plastic leaded chip carrier copyright ? 2002 transwitch corporation transwitch and txc are registered trademarks of transwitch corporation digital cross-connect equipment remote terminals terminal interface for multiplexers/demultiplexers switching systems csu/dsu data sheet proprietary transwitch corporation information for use solely by its customers applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
data sheet - 2 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers table of contents section page table of contents.............................................................................................................. ................ 2 list of figures................................................................................................................ .................... 2 block diagram.................................................................................................................. ................. 3 block diagram description...................................................................................................... .......... 4 pin diagram .................................................................................................................... .................. 5 pin descriptions ............................................................................................................... ................. 6 absolute maximum ratings ....................................................................................................... ..... 11 thermal characteristics ........................................................................................................ .......... 11 power requirements............................................................................................................. .......... 11 input and output parameters.................................................................................................... ...... 12 timing characteristics......................................................................................................... ............ 14 operation ...................................................................................................................... .................. 19 power supply, ground and pll connections ......................................................................... 19 overview ....................................................................................................................... ........... 21 jitter and interfering tone tolerances ..................................................................................... 23 hdb3 patterns.................................................................................................................. ....... 26 examples of transmit input and output data (34368 kbit/s operation) .................................. 27 packaging ...................................................................................................................... ................. 28 ordering information ........................................................................................................... ............ 29 related products............................................................................................................... .............. 29 standards documentation sources ................................................................................................ 30 list of data sheet changes ..................................................................................................... ....... 32 documentation update registration form* ............................................................................... 35 * please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the lat est available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1. mrt TXC-02050C block diagram.......................................................................................... 3 2. mrt TXC-02050C pin diagram ............................................................................................. 5 3. pulse mask at the 34368 kbit/s interface .............................................................................. 14 4. pulse mask at the 8448 kbit/s interface ................................................................................ 15 5. pulse mask at the 6312 kbit/s interface ................................................................................ 15 6. nrz transmit input timing................................................................................................... 16 7. nrz receive output timing ................................................................................................. 16 8. p and n rail transmit input timing ...................................................................................... 17 9. p and n rail receive output timing .................................................................................... 18 10. mrt power supply, ground and pll connections.............................................................. 19 11. ground plane of application circuit board ........................................................................... 20 12. line side input circuit..................................................................................................... ...... 21 13. line side output circuit outline - no socket (34368 kbit/s) ................................................. 22 14. line side output circuit outline - socket (34368 kbit/s)....................................................... 22 15. line side output circuit outline (8448 and 6312 kbit/s)....................................................... 23 16. mrt jitter tolerance at 34368 kbit/s .................................................................................... 23 17. mrt jitter tolerance at 8448 kbit/s ...................................................................................... 24 18. mrt jitter tolerance at 6312 kbit/s ...................................................................................... 24 19. examples of hdb3 coding ................................................................................................... 2 6 20. examples of transmit input and output data (34368 kbit/s operation) ................................ 27 21. mrt TXC-02050C 44-pin plastic lead chip carrier............................................................ 28
data sheet - 3 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers block diagram figure 1. mrt TXC-02050C block diagram line side terminal side eqb0 eqb1 low gnda agfil rxlos rxais rxdis rp/rd rn clko clko tp/td tn clki txloc dck di1 di2 tpo tno equalization network agc clock recovery hdb3 decoder i/o hdb3 encoder output driver detector + - clk vagc vcoc pllc and lq cv + - clk vdd gndd lbkrx cv lqlty berck pnenb dck + - clk lbktx circuits txais indicator receive (line) loopback transmit (terminal) loopback
data sheet - 4 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers block diagram description on the line side, a symmetrical bipolar signal is applied to the input signal pin (di1), which requires an exter- nal 75 ? termination. di2 is a dc reference voltage output which serves as an ac ground. equalization for various lengths of cable having a f attenuation characteristic is compensated by setting the states of the eqb0 and eqb1 signal leads. the equalization network block is connected to an agc block which has approximately a 20 db dynamic range. the agc has separate voltage and ground leads for noise immunity, and uses an external capacitor as part of an agc filter. the agc output is connected to the clock recovery block. the clock recovery block contains a phase-locked loop and supporting logic to generate a clock signal from the line signal. the signal lead low selects the appropriate circuit in the clock recovery block for the operat- ing frequency and provides input attenuation for the receive line signal. the line input is monitored for loss of signal, with an alarm indication provided on the rxlos signal lead. the clock recovery block requires an external reference clock at the operating frequency (dck). the reference clock is also used for generating and sending a receive alarm indication signal (ais). the generation and sending of ais for recovered data is con- trolled by the rxais signal lead. the output of the clock recovery block is connected to the hdb3 decoder block, when enabled, or directly to the i/o circuits block. when the decoder is enabled, indications of coding violation errors, other than the nor- mal hdb3 zero substitution codes, are provided as pulses on the signal lead labeled cv by the cv detector and lq indicator block. examples of hdb3 coding and violations are shown in figure 19. an external clock (berck) is used to generate a 10-second sampling window for detecting a 10 -6 or greater error rate. the resulting line quality indication is provided on the output signal lead lqlty. two terminal side interfaces are provided, a positive and negative rail (rp and rn) or nrz (rd) interface. the selection is determined by the state placed on the input signal lead pnenb . when a low is applied to this sig- nal lead, the hdb3 decoder and hdb3 encoder blocks are bypassed, and the terminal side i/o is a positive and negative rail interface. when a high is applied to the signal lead, an nrz interface is provided. data is clocked out of the mrt on negative edges of the clock output signal (clko). receive data and the clock sig- nals are disabled, and forced to a high impedance state, by placing a low on the receive disable input lead (rxdis ). for a receive positive and negative rail interface, an inverted clock output signal (clko ) is also pro- vided. the terminal side interface for the transmitter can either be positive and negative rail (tp and tn) or nrz (td) data depending on the state of the common control input lead pnenb (see figure 20 for examples). data is clocked into the mrt on positive transitions of the clock signal (clki). the input clock is monitored for the loss of clock. when the input clock remains high or low, txloc will be set low. the mrt also provides the capabil- ity to generate and insert ais (all ones signal), independent of the transmit data. a low placed on the txais input lead enables the transmit ais generator. two loopbacks are provided, transmit loopback and receive loopback. transmit loopback connects the data path from the transmitter output driver block to the clock recovery block, and disables the external receiver input. transmit loopback is activated by placing a low on the lbktx input signal lead. receive loopback con- nects the receive data path to the transmit output circuits and disables the transmit input. receive loopback is activated by placing a low on the lbkrx input signal lead. for 6 mbit/s operation, the mrt should be operated in the p and n rail mode, bypassing the hdb3 decoder/ encoder. when the mrt is used with the transwitch jt2f device at this bit rate, the jt2f can provide either b6zs or b8zs encoding and decoding.
data sheet - 5 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers pin diagram figure 2. mrt TXC-02050C pin diagram mrt (top view) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 pllc gndd clko clko rp/rd rn gndd vdd dck pnenb vcoc di1 di2 gnda gndd tno tpo vdd gndd vdd clki gndd tp/td tn vdd txais gndd gndd txloc rxais berck lqlty gndd eqb0 eqb1 low lbktx lbkrx vag c agfil rxdis rxlos cv vdd pin diagram TXC-02050C
data sheet - 6 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers pin descriptions power supply and ground *note: i = input; o = output; p = power. line side i/o * see input and output parameters section for digital type definitions. terminal side i/o symbol pin no. i/o/p* type name/function vdd 10,18,35, 37,42 p vdd: v dd , +5 volt supply, 5%. gndd 1,6,11,16,32, 36,39,44 p digital ground: 0 volts reference. vagc 23 p agc vdd: +4.3 volt supply, derived from v dd using 1n914 or 1n4148 diode (see figure 10). gnda 31 p analog groun d: 0 volts reference. symbol pin no. i/o/p type * name/function di1 29 i analog data in 1: hdb3 or b8zs encoded bipolar receive data input. di2 30 o analog data in 2: dc voltage reference for data input di1. the mrt uses an internally generated voltage refer- ence as an ac ground for the received data input. an external 0.1 f capacitor, in parallel with a 10 f/6.3 v tantalum capacitor, is connected between this pin and ground. no other connection should be made to this pin. tno 33 o ttl24ma transmit negative out: line transmit negative; output is active high. tpo 34 o ttl24ma transmit positive out: line transmit positive; output is active high. symbol pin no. i/o/p type name/function rn 12 o ttl4ma (tristate) receive negative: when pnenb is low, the hdb3 codec is bypassed and n-rail (rn) data is provided on this pin. when pnenb is high or rxdis is low, this pin is forced to a high impedance state (disabled). rp/rd 13 o ttl4ma (tristate) receive positive/receive data: when pnenb is low, the hdb3 codec is bypassed and p-rail (rp) data is provided on this pin. when pnenb is high, nrz data (rd) is provided. when rxdis is low, this pin is forced to a high impedance state (disabled).
data sheet - 7 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers alarm signal outputs clko 14 o cmos8ma (tristate) clock out inverted: receive inverted clock output. positive and negative rail receive data is clocked out on the rising edge. when pnenb is high or rxdis is low, this pin is forced to a high impedance state (disabled). clko 15 o cmos8ma (tristate) clock out: receive clock output. receive positive and negative rail and nrz data is clocked out on the falling edge. when rxdis is low, this pin is forced to a high impedance state (disabled). clki 38 i ttlr clock in: transmit clock input for p and n rail and nrz data. transmit data is clocked into the mrt on the rising edge. this clock must have a frequency accuracy of 20 ppm for the 34368 kbit/s operation and 30 ppm for the 6312/8448 kbit/s operation (ref: itu-t recom- mendation g.703). the duty cycle requirement for this clock signal is (50 5) %, measured at the 1.4v ttl threshold level. tp/td 40 i ttl transmit positive/transmit data: when pnenb is low, the hdb3 codec is bypassed and transmit p-rail (tp) data is applied to this pin. when pnenb is high, nrz transmit data (td) is applied. tn 41 i ttl transmit negative: when pnenb is low, the hdb3 codec is bypassed and transmit n-rail (tn) is applied to this pin. when pnenb is high, this input is disabled. symbol pin no. i/o/p type name/function txloc 2 o ttl2ma transmit loss of clock: active low output. a transmit loss of clock alarm occurs when the transmit clock input (clki) is stuck high or low for about 500 clock cycles. recovery occurs on the first input clock transition. dck is required for proper operation. lqlty 5 o ttl2ma line quality: this signal represents an estimate of the line quality which is determined by counting coding vio- lations for 34 (8) mbit/s operation. if the line error rate exceeds a 10 -6 threshold during a 10 (40) second inter- val, lqlty goes active high. lqlty is active low when coding violations do not exceed the 10 -6 threshold in a 10 (40) second interval. the output on this pin is only valid when the appropriate clock signal is applied to berck. it should be disregarded in the p and n mode of operation or in 6 mbit/s operation. symbol pin no. i/o/p type name/function
data sheet - 8 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers mrt control leads cv 19 o ttl2ma coding violation: active high output. a coding violation pulse occurs when an hdb3 coding violation is detected in the received line data input. a coding violation is not part of the hdb3 zero-substitution code. a coding viola- tion occurs because of noise or other impairments affecting the line signal. the output of this pin should be disregarded in the p and n mode. rxlos 20 o ttl2ma receive loss of signal: active low output. a receive loss of signal occurs when the input data is zero for 40-50 s. recovery occurs when the receive signal returns. symbol pin no. i/o/p type name/function rxais 3icmosr receive alarm indication signal: when rxais is low, the mrt generates ais (all ones signal) for the terminal side receive output data. the line side receive data path is disabled. the reference clock (dck) provides the clock source required for generating ais. berck 4 i ttlr bit error rate clock: this clock establishes the time base for estimating the coding violation error rate. for 34 mbit/s operation the clock frequency must be 6 khz, and for 8 mbit/s operation the clock frequency must be 1.5 khz. this pin should be left open for p and n mode operation. pnenb 8icmosr p and n enable: when pnenb is low, the p and n rail interface is enabled, and the hdb3 codec is bypassed. when pnenb is high, the terminal side i/o data is nrz and the hdb3 codec is enabled. this pin must be held low for 6 mbit/s operation. dck 9 i ttl reference clock: operating frequency reference clock. for receive signal clock recovery, 200 ppm frequency accuracy is adequate. if the transmit and receive ais features are used, the frequency accuracy must be 20 ppm for 34368 kbit/s and 30 ppm for 8448 and 6312 kbit/s operation. the duty cycle requirement for this clock signal is (50 5) % as measured at the 1.4v ttl threshold level. rxdis 21 i cmosr receive disable: when rxdis is low, the receive side of the mrt is disabled and the rn, rp/rd, clko and clko output leads are forced to a high impedance state. symbol pin no. i/o/p type name/function
data sheet - 9 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers note 2: for 6 mbit/s operation, setting the equalizer for long cable length while having a short cable will cause an error in the recovered clock frequency. the recovered clock frequency will not be 6.312 mhz. lbkrx 24 i cmosr loopback receive: when lbkrx is low, the mrt loops back receive data as transmit data. the receive data is also sent to the terminal side, but the transmit data input on the terminal side is disabled (see note 1). lbktx 25 i cmosr loopback transmit: when lbktx is low, the mrt loops back transmit data as receive data. the transmit data is sent on the line side, but the receive data input on the line side is disabled (see note 1). note 1: setting lbktx and lbkrx low simultaneously will cause invalid outputs at the receive terminal and transmit line ports. low 26 i cmosr low frequency: when low is low, the mrt enables equalization and input attenuator settings for 6312 or 8448 kbit/s operation. when low is high, the settings for 34368 kbit/s operation are enabled. this lead also controls the clock recovery high/low frequency range cir- cuit. eqb1 eqb0 27 28 i i cmosr equalizer bit 1: msb of equalizer setting. equalizer bit 0: lsb of equalizer setting. the equalizer setting depends on cable length (attenuation) as shown in the following tables. for 34 mbit/s operation: equivalent eqb1 eqb0 cable attenuation @ f * att 734a cable 1 1 0db < cable < 5.7db 0 - 550 ft. 1 0 4.1db < cable < 12db 400 - 1150 ft. 0 0 5.7db < cable < 14db 550 - 1350 ft. 0 1 6.8db < cable <14 db 650 - 1350 ft. for 8 mbit/s operation: 1 1 0db < cable < 3.5db 0 - 550 ft. 1 0 3.0db < cable < 6.5db 500 - 1100 ft. 0 0 3.6db < cable < 6.8db 700 - 1350 ft. equivalent for 6 mbit/s operation (see note 2): att 734a cable 1 1 0db < cable < 2.4db 0 - 550 ft. 1 0 2.4db < cable < 5.1db 500 - 1100 ft. 0 0 3.1db < cable < 6.0db 700 - 1350 ft * f = 1/2 the bit rate txais 43 i cmosr transmit ais: when txais is low, the mrt sends an ais (all ones signal) for the line side transmit output data. the terminal side transmit data path is disabled. the reference clock (dck) provides the clock required for generating ais. equivalent symbol pin no. i/o/p type name/function
data sheet - 10 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers pins with external components symbol pin no. i/o/p type name/function vcoc 7 i analog voltage controlled oscillator capacitor: for 6, 8, and 34 mbit/s operation, a 470 ohm 5% 1/8 watt resistor is connected in series with a 0.1 f 10% capacitor from this pin to ground. this component is used in the phase- locked loop filter. pllc 17 i analog phase-locked loop capacitor: 0.1 f 10% ceramic disk capacitor connected to ground. agfil 22 i analog automatic gain filter: for 6 , 8, and 34 mbit/s opera- tion, a 0.1 f 10% ceramic disk capacitor is con- nected from this pin to ground.
data sheet - 11 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers absolute maximum ratings *note: operating conditions exceeding those listed in absolute maximum ratings may cause permanent failure. expo- sure to absolute maximum ratings for extended periods may impair device reliability. thermal characteristics power requirements * with inputs switching and outputs terminated. parameter symbol min * max * unit supply voltage v dd -0.3 +7.0 v agc supply voltage v agc -0.5 +6.5 v dc input voltage v in -0.5 v dd + 0.5 v continuous power dissipation p c 750 mw ambient operating temperature t a -40 85 o c operating junction temperature t j 125 o c storage temperature range t s -55 150 o c parameter min typ max unit test conditions thermal resistance: junction to ambient 46 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v v agc v dd - 0.3 v dd - 0.62 v derived from v dd via a 1n914 or 1n4148 diode. i dd 100 ma v dd = 5.25v i agc 20 ma v agc = 4.63v p dd 525 mw v dd = 5.25v * p agc 93 mw v agc = 4.75v *
data sheet - 12 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers input and output parameters input parameters for ttl input parameters for ttlr note: input has a 100k (nominal) internal pull-up resistor. input parameters for cmosr note: input has a 100k (nominal) internal pull-up resistor. output parameters for ttl2ma parameter min typ max unit test conditions v ih 2.0 v dd +0.3 v 4.75 < v dd < 5.25 v il -0.3 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 5.5 pf parameter min typ max unit test conditions v ih 2.0 v dd +0.3 v 4.75 < v dd < 5.25 v il -0.3 0.8 v 4.75 < v dd < 5.25 input leakage current 50 120 av dd = 5.25 input capacitance 5.5 pf parameter min typ max unit test conditions v ih 2.0 v dd +0.3 v 4.75 < v dd < 5.25 v il -0.3 0.8 v 4.75 < v dd < 5.25 input leakage current 50 120 av dd = 5.25 input capacitance 5.5 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -1.0 ma v ol 0.4 v v dd = 4.75; i ol = 2.0 ma i ol 2.0 ma i oh -1.0 ma
data sheet - 13 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers output parameters for ttl4ma output parameters for ttl24ma output parameters for cmos8ma t rise 5.5 12.5 18.2 ns c load = 15pf t fall 2.3 4.4 6.5 ns c load = 15pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0 ma v ol 0.4 v v dd = 4.75; i ol = 4.0 ma i ol 4.0 ma i oh -2.0 ma t rise 2.8 6.5 9.2 ns c load = 15 pf t fall 1.3 2.3 3.4 ns c load = 15 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -12.0 ma v ol 0.4 v v dd = 4.75; i ol = 24.0 ma i ol 24.0 ma i oh -12.0 ma t rise 0.8 1.4 1.8 ns c load = 25 pf t fall 0.5 0.8 1.0 ns c load = 25 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -8.0 ma v ol 0.4 v v dd = 4.75; i ol = 8.0 ma i ol 8.0 ma i oh -8.0 ma t rise 1.3 2.4 3.8 ns c load = 25 pf t fall 1.1 1.8 2.5 ns c load = 25 pf parameter min typ max unit test conditions
data sheet - 14 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers timing characteristics detailed timing diagrams for the mrt are illustrated in figures 3 through 9. all output times are measured with maximum load capacitance appropriate for the pin type. timing parameters are measured at voltage levels of (v ih + v il )/2 for input signals or (v oh + v ol )/2 for output signals. line side timing characteristics the line side timing characteristics of the mrt are designed so that the line output at the transformer output meets the pulse shapes specified in itu-t rec. g.703 for 34 and 8 mbit/s operation and the ntt technical reference for high-speed digital leased circuit services for 6 mbit/s operation. the pulse masks for each of the three modes of operation are shown in figures 3, 4, and . refer to the corresponding standard cited in each case for further details regarding the interface. the output circuits to be used are shown in figures 12, 13 and 14. figure 3. pulse mask at the 34368 kbit/s interface 17 ns (14.55 + 2.45) v 1.0 0.5 0 8.65 ns (14.55 - 5.90) 14.55 ns 12.1 ns (14.55 - 2.45) 24.5 ns (14.55 + 9.95) 29.1 ns (14.55 + 14.55) nominal pulse 0.1 0.1 0.1 0.1 0.1 0.1 reference: itu-t recommendation g.703 0.2 0.2 0.2
data sheet - 15 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers figure 4. pulse mask at the 8448 kbit/s interface figure 5. pulse mask at the 6312 kbit/s interface 69 ns (59 + 10) v 2.370 1.185 0 35 ns (59 - 24) 59 ns 49 ns (59 - 10) 100 ns (59 + 41) 118 ns (59 + 59) nominal pulse 0.237 0.237 0.237 0.237 0.237 0.237 0.474 reference: itu-t recommendation g.703 0.474 0.474 pulse amplitude a nominal pulse shape (0,2) (0,1) b c d e (0,0) (4,0) time f g h i horizontal axis 20 ns/div vertical axis 1 v/div reference: ntt technical reference for high-speed digital leased circuit services coordinates of each point a : (0.0, 2.3) f : (0.0, 1.7) b : (2.4, 2.3) g : (0.4, 1.7) c : (2.4, 1.0) h : (1.6, 0.9) d : (3.2, 0.3) i : (1.6, 0.3) e : (4.0, 0.3) 2.0v peak 50% width (third edition, 1990)
data sheet - 16 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers terminal side timing characteristics figure 6. nrz transmit input timing figure 7. nrz receive output timing see notes on next page. parameter symbol min typ max unit clki clock period t cyc (note 2) ns clki duty cycle (t pwh /t cyc ) (note 1) -- 45 55 % tp,td set-up time to clki t su 3ns tp,td hold time after clki t h 2ns parameter symbol min typ max unit clko clock period t cyc (note 2) ns clko duty cycle (t pwh /t cyc ) (note 1) -- 45 55 % rp,rd output delay after clko t od(1) -5 5 ns cv output delay after clko (note 3) t od(2) -5 5 ns data valid data valid data valid clki 1.4v tp,td t su t pwh t h t cyc clko rp,rd cv t pwh t cyc t od(1) t od(2)
data sheet - 17 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers notes: 1. clko symmetry is measured about the 50% amplitude point. 2. 158.4 ns for 6312 kbit/s; 118.4 ns for 8448 kbit/s; 29.10 ns for 34368 kbit/s. 3. the cv pulse occurs at the same time as the errored bit is presented at the output. figure 8. p and n rail transmit input timing notes: 1. clki symmetry is measured about the 1.4vdc threshold in order to assure symmetric output waveforms. 2. 158.4 ns for 6312 kbit/s; 118.4 ns for 8448 kbit/s; 29.10 ns for 34368 kbit/s. parameter symbol min typ max unit clki clock period t cyc (note 2) ns clki duty cycle (t pwh /t cyc ) (note 1) -- 45 55 % tp,td & tn set-up time to clki t su 3ns tp,td & tn hold time after clki t h 2ns data va lid data vali d data valid clki 1.4v tp,td t su t pwh t cyc t h data vali d data valid data valid tn
data sheet - 18 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers figure 9. p and n rail receive output timing notes: 1. clko symmetry is measured about the 50% amplitude point. 2. 158.4 ns for 6312 kbit/s; 118.4 ns for 8448 kbit/s; 29.10 ns for 34368 kbit/s. parameter symbol min typ max unit clko clock period t cyc (note 2) ns clko duty cycle (t pwh /t cyc ) (note 1) -- 45 55 % clko output delay after clko t od(1) 2ns rp, rd and rn output delay after clko t od(2) -5 6 ns clko rp, rd t pwh t cyc t od(1) t od(2) rn clko
data sheet - 19 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers operation power supply, ground and pll connections figure 10. mrt power supply, ground and pll connections the mrt device has separate power supply pins labeled vdd and vagc. the vagc supply pin is connected to the internal agc amplifier and is derived from the vdd supply as indicated in figure 10. separate bypass networks must be used for connecting the vdd and vagc supply pins on the mrt to +5v. the bypass network on the vagc pin consists of a 1n4148 or 1n914 diode, a ferrite bead and a 10 microfarad 6.3 volt (tantalum) capacitor connected to analog ground in parallel with a 0.1 microfarad capacitor, as shown in figure 10. transwitch recommends that the 0.1 microfarad decoupling capacitors be of rf quality and that they be con- nected in close proximity to the device. the recommended ground plane for the mrt device is a common ground plane for both analog and digital ground. the ground plane beneath and approximately 0.25" beyond the physical dimensions of the mrt needs to be separated into analog and digital grounds by notching approximately 25 mils of the copper ground plane, as shown in figure 11. additional mrt application design considerations are discussed in transwitch application note an-517 ?design considerations for use of the mrt device with the e2/e3f device.? TXC-02050C gndd gndd gndd gndd gndd gndd gndd gndd gnda vdd vdd vdd vdd vdd vag c 10/6.3v 10/6.3v 1 6 11 16 32 36 39 44 23 31 10 18 35 37 42 v dd , +5v + + 1n914 or 1n4148 a a a d d d d d d d d ferrite bead *(see note 2) a a = analog ground d = digital ground legend: notes: 1. all capacitors are 0.1 microfarad unless other- wise specified. 2. ferrite bead is part number 2743002111 of fair rite corp., walkill, ny, (914) 895-2055 or equivalent. vcoc 7 a pllc 17 a agfil 22 a capacitor removed 470
data sheet - 20 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers figure 11. ground plane of application circuit board d 40 6 29 39 17 7 28 18 1 a legend: --- 25 mil notching of ground plane under device to separate analog (a) and digital (d) ground areas d d
data sheet - 21 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers overview line side input impedance the input impedance of the mrt is a function of the state of the low lead and the operating rate. the table below lists the input impedance of the mrt at the operating line rates (which are 1/2 the bit rates). line side input sensitivity the input voltage sensitivity of the mrt depends on the state of the low lead as shown in the table below. line side input circuit the circuit shown in figure 12 illustrates the components required for operating the mrt device at 34368, 8448 or 6312 kbit/s. the 1:1 transformer should have a frequency response of 0.2 mhz < f < 80 mhz with an insertion loss of 1 db, maximum (suitable devices include coilcraft part no. wb-1010 and pulse engineering part no. pe-65966). this gives return loss and isolation voltage values that meet or exceed requirements. figure 12. line side input circuit mrt input impedance condition minimum input impedance, | z | low = 1, line rate = 17184 khz (e3) 1260 ohms low = 0, line rate = 4224 khz (e2) 2390 ohms low = 0, line rate = 3156 khz (jt2) 3670 ohms mrt input sensitivity low lead rate, mbit/s input sensitivity (peak volts) min max 0 6/8 (jt2/e2) 0.5 2.7 134 (e3) 0.15 1.1 TXC-02050C mrt device 1 : 1 receive data input 10/6.3 10/6.3 0.1 0.1 75 5% + + 29 30
data sheet - 22 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers line side output characteristics the line side output of the mrt switches from ?rail to rail? on both of its output leads, tpo and tno. this pro- vides the maximum voltage swing, and makes the output voltage depend on the +5 volt power supply input to the chip. the external circuit design must therefore be done with care in order to assure meeting the amplitude requirements. line side output circuits figure 13 illustrates the output circuit required for operating the mrt device in a 34368 kbit/s application with- out a socket. the transformer and resistors shown assure that the output waveform meets the itu-t mask for 34368 kbit/s transmission and that the mrt device is operated within the current limits of the ttl24ma output parameters. the 1:2 transformer should have a frequency response of 0.2 mhz < f < 80 mhz with an insertion loss of 1db, maximum (suitable devices include coilcraft part no. wb-1040 and pulse engineering part no. pe-65969). figure 13. line side output circuit outline - no socket (34368 kbit/s) figure 14 shows a variation of the circuit in figure 13. this circuit improves performance in applications when a plastic device is mounted in a socket. the additional low-pass filter compensates for possible overshoot caused by inductance created by the device/socket interface. the 1:2 transformer should have a frequency response of 0.2 mhz < f < 80 mhz with an insertion loss of 1db, maximum (suitable devices include coilcraft part no. wb-1040 and pulse engineering part no. pe-65969). figure 14. line side output circuit outline - socket (34368 kbit/s) the peak voltage and current output requirements for 6312 and 8448 kbit/s operation are different from those for 34368 kbit/s operation. figure 15 illustrates the output circuit required for 6312 kbit/s and 8448 kbit/s opera- tion. the 1:1 transformer should have a frequency response of 0.2 mhz < f < 80 mhz with an insertion loss of 1db, maximum (suitable devices include coilcraft part no. wb-1010 and pulse engineering part no. pe-65966). the transformer, drivers and resistors assure that the output waveform meets the pulse mask requirements for these rates and that the mrt device is operated within the current limits of the ttl24ma out- put parameters. TXC-02050C mrt device 1 : 2 150 150 transmit data output 34 33 TXC-02050C mrt device 1 : 2 75 75 transmit data output 100 100 18 pf 18 pf 34 33
data sheet - 23 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers figure 15. line side output circuit outline (8448 and 6312 kbit/s) jitter and interfering tone tolerances the jitter measurements described in this subsection are performed using an anritsu model me502b digital transmission analyzer, or equivalent. jitter tolerance itu-t recommendations g.823 and jt-g703 specify that network equipment must be able to accommodate and tolerate levels of jitter up to certain specified limits. the mrt accommodates and tolerates more input jitter than the level of input jitter specified by these recommendations. with input jitter applied to the mrt line side receive input di1 (pin 29), the mrt properly recovers clock, decodes the signal, and outputs error-free nrz data over (and beyond) the itu-t ranges specified for jitter input and frequency. performance characteristics are shown below in figure 16 (34368 kbit/s operation), figure 17 (8448 kbit/s operation) and figure 18 (6312 kbit/s operation). figure 16. mrt jitter tolerance at 34368 kbit/s TXC-02050C mrt device 1 : 1 r1 r2 transmit data output 74act11244 34 33 for 8448 kbit/s operation: r1 and r2 = 27 ? for 6312 kbit/s operation: r1 and r2 = 36 ? or equivalent 10.0 0.1 10hz 100hz 1khz 100khz log scale 30 khz measured minimum requirement log scale acceptance range 1mhz 10khz 1.0 itu-t rec. g.823 limit frequency 1.5 0.15 notes: unit interval (ui) = 1/(system clock frequency) = 29.10 ns input jitter (ui peak- peak) test conditions: v dd =5v, t a =25 c, hdb3 coding, 2 23 -1 data pattern
data sheet - 24 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers figure 17. mrt jitter tolerance at 8448 kbit/s figure 18. mrt jitter tolerance at 6312 kbit/s 10.0 0.1 10hz 100hz 1khz 100khz 10 khz measured minimum requirement log scale acceptance range 1mhz 10khz 1.0 itu-t rec. g.823 limit frequency 1.5 0.2 notes: unit interval (ui) = 1/(system clock frequency) = 118.4 ns 3k 400 20 test conditions: v dd =5v, t a =25 c, hdb3 coding, 2 15 -1 data pattern input jitter (ui peak- peak) log scale 10 0.1 10hz 100hz 1khz 20khz measured minimum requirement log scale 40khz 10khz frequency 1 0.1 notes: unit interval (ui) = 1/(system clock frequency) = 158.4 ns test conditions: v dd =5v, t a =25 c, b8zs coding, 2 15 -1 data pattern input jitter (ui peak- peak) log scale (jt-g703) 200hz 0.13 0.3 acceptance range 50hz 2.5khz 5 60khz
data sheet - 25 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers maximum output jitter in absence of input jitter itu-t recommendation g.823 specifies that it is necessary to restrict the amount of jitter generated by individ- ual equipment at an output port. the amount of jitter allowed is dependent on the application in which the equipment is used. for example, in a repeater application the recovered clock will be used for the transmit clock. the recovered clock will have jitter due to the sending transmitter and to clock recovery of distorted data. the jitter will be additive through each repeater. therefore, it would be necessary to add a dejitter buffer (a pll with a very low bandwidth, usually using a vcxo) to reduce the jitter in the recovered clock before using it as a transmit clock. for the mrt in non-repeater applications, the maximum output jitter measurement is made on the transmit path. the recovered clock output jitter is unimportant as long as proper clocking of following devices in possible (with the exception of the above-mentioned repeater applications). the transmit clock in these cases is coming from a device such as a framer whose clock is derived from the local oscillator on the board. to make this mea- surement, apply a signal with known jitter characteristics to the transmitter inputs and measure the jitter at the transmitter outputs. in the absence of applied jitter, the transmit path of the mrt introduces a maximum 0.05 unit intervals (uis) peak-to-peak jitter over the following frequency ranges: at 6.312 mbit/s: 10 hz to 160 khz at 8448 kbit/s: 20 hz to 400 khz at 34368 kbit/s: 100 hz to 800 khz this operation is with the mrt terminated by the external components (and component values) specified in the pin description table for pin 7 (vcoc), pin 17 (pllc), and pin 22 (agfil). jitter transfer transfer of jitter through individual equipment is characterized by the relationship between the applied input jit- ter and the resulting output jitter as a function of frequency. itu-t recommendation g.823 specifies that it is important to restrict jitter gain. figure 4 of g.823 shows a typical jitter transfer characteristic. note that a small jitter gain is allowed. british standard 6328: section 8.1, 1990 gives the allowable gain as 0.5 db. with applied input jitter at the mrt receive input terminals, the maximum mrt receive output jitter is not greater than the level of input jitter plus a maximum of 0.05 ui peak-to-peak jitter in the range of 10 hz to 160 khz for 6 mbit/s, 20 hz to 400 khz for 8 mbit/s, and 100 hz to 800 khz for 34 mbit/s. these values are mea- sured by applying a controlled, sinusoidal jitter signal to pins di1 and di2, then measuring the jitter at the receiver output (i.e., clko). this operation is with the same mrt external terminations as described in the maximum output jitter section above. interfering tone tolerance the mrt will properly recover clock and present error-free output to the receive terminal side interface in the presence of a prbs interfering tone with the same data sequence as the data input while operating at 6, 8 or 34 mbit/s, as specified in the following table:
data sheet - 26 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers *prbs = pseudo-random binary sequence hdb3 patterns e = indicates even number of pulses since last violation (v) od = indicates odd number of pulses since last violation (v) v = intentional violation of alternating plus and minus pulses used for 1?s b = pulse that follows the normal alternating bipolar coding scheme four zeros are replaced with b00v or 000v; the substitution choice is made so that the number of pulses between violations (v?s) is odd; note that sequential violations are of opposite polarity so the net charge on the transmission medium is zero. figure 19. examples of hdb3 coding prbs* interfering tone tolerance data rate (kbit/s) tone rate (kbit/s) maximum tone level data sequence requirement 34368 34368 100ppm -11.5 db 2 23 - 1 - 20 8448 8448 100ppm -14.5 db 2 15 - 1 - 18.5 10 10 10 10 10 10 10 10 1 00 11 00 00 00 11 11 11 11 b v od v e od v v b e od 101000011000010000000 hdb3 hdb3 hdb3 0
data sheet - 27 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers examples of transmit input and output data (34368 kbit/s operation) unencoded nrz data (0 1 0 1 0 .....) encoded nrz p & n data (0 1 0 1 0 ....) tpo, tno, clki and txcable are the same as in the unencoded nrz case. figure 20. examples of transmit input and output data (34368 kbit/s operation) tpo tno clki tp/td tn txcable mrt 1:1 111 000 tp/td tn tpo tno clki txcable 0 0 0 0 0 0 5 1 1 1 1 -1 rz pulse bipolar rz signal t 0 1 0 tp/td tn 0 0 5 5 1 11 1
data sheet - 28 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers packaging the mrt device is packaged in a 44-pin plastic leaded chip carrier suitable for socket or surface mounting, as illustrated in figure 21. all dimensions shown are in inches and are nominal unless otherwise noted. figure 21. mrt TXC-02050C 44-pin plastic lead chip carrier transwitch 40 6 29 39 17 7 28 18 0.500 sq. 0.650 sq. 0.075 0.149 0.170 bottom view top view 40 6 29 39 17 7 28 18 1 1 0.690 sq. 0.050 typ 0.015 typ
data sheet - 29 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers ordering information part number: TXC-02050Cipl 44-pin plastic leaded chip carrier related products txc-03701 e2/e3f framer vlsi device. the e2/e3 framer directly interfaces with the mrt and provides multi-mode framing for itu-t rec. g.751/g.753 (34368 kbit/s) or itu-t rec. g.742/g.745 (8448 kbit/s) signals. txc-03702 jt2f framer vlsi device. the jt2f framer directly interfaces with the mrt and provides framing for itu-t rec. g.704 (6312 kbit/s) signals. txc-06125 xbert vlsi device (bit error rate generator / receiver). programmable multi- rate test pattern generator and receiver in a single chip with bit-serial, nibble-parallel or byte- parallel interface capability. txc-21055 mrt evaluation board. a complete ready-to-use single board that demonstrates the functions and features of the mrt line interface vlsi device.
data sheet - 30 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 25 west 43 rd street fax: (212) 398-0023 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 404 balboa street tel: (415) 561-6275 san francisco, ca 94118 fax: (415) 561-6120 web: www.atmforum.com atm forum europe office kingsland house - 5 th floor tel: 20 7837 7882 361-373 city road fax: 20 7417 7500 london ec1 1pq, england atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (303) 397-7956 (outside u.s.a.) 15 inverness way east fax: (303) 397-2740 englewood, co 80112 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 00 fax: 4 93 65 47 16 650 route des lucioles web: www.etsi.org 06921 sophia-antipolis cedex, france
data sheet - 31 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (903) 769-3818 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5852 fax: 22 730 5853 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 fax: (215) 697-1462 building 4 / section d web: www.dodssp.daps.mil 700 robbins avenue philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 5440 sw westgate dr., #217 tel: (503) 291-2569 (outside u.s.a.) portland, or 97221 fax: (503) 297-1090 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-2673 (within u.s.a.) attention - customer service tel: (732) 699-2000 (outside u.s.a.) 8 corporate place rm 3a184 fax: (732) 336-2559 piscataway, nj 08854-4157 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunication technology committee tel: 3 3432 1551 fax: 3 3432 1553 hamamatsu-cho suzuki building web: www.ttc.or.jp 1-2-11, hamamatsu-cho, minato-ku tokyo 105-0013, japan
data sheet - 32 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers list of data sheet changes this change list identifies those areas within the updated mrt data sheet that have technical differences rela- tive to the superseded mrt data sheet: updated mrt ?c? data sheet: edition 1, may 2002 superseded mrt data sheet: edition 3, april 1994 the page numbers indicated below of the updated data sheet include changes relative to the superseded data sheet. page number of updated data sheet summary of the change all changed edition number and date. all changed gnd to gndd. 1 made changes to items 3, 5, 6, 7 and 10 of the feature list. 1 added items 9, 11 and 12 to the feature list. 1 modified the first paragraph of description section. changed patent infor- mation. 2 added table of contents and list of figures. 3 modified figure 1 and added product number to the figure title. 4 made changes to block diagram description section. 5 added product number to the figure title 2. 6 made changes to name/function column for vdd, gndd, vagc, gnda, tno and tpo. 6 added a note below the table to explain type column heading for ?line side i/o? section. 6-7 made changes to type and name/function columns for rn, rp/rd, clko and clko. 7-10 made changes to name/function column for clki, txloc , lqlty, rxlos , dck, low , eqb1, eqb0, vcoc and agfil. 10 made changes to i/o/p column for vcoc, pllc, agfil and added note below the table. 11 added test conditions column to the second table. made changes to v agc row of the last table. changed test condition for i agc and changed max for p agc to the last table. changed in first table max. operating junction temperature. added a note below the table.
data sheet - 33 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers 12 added max for v ih and min for v il of the first three tables. 14-18 made changes to timing characteristics section. 19-24 made changes to operation section. removed capacitor from pin 31 and note 3 from figure 10. updated jitter requirements in figure 18. 28 made minor changes to packaging section. 29 added item 3 to the related products section. 30-31 updated the standards documentation sources section. 32-33 updated list of data sheet changes. 35 added documentation update registration form. page number of updated data sheet summary of the change transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
- 34 of 36 - transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453
data sheet - 35 of 36 - TXC-02050C-mb ed. 1, may 2002 mrt TXC-02050C proprietary transwitch corporation information for use solely by its customers documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ___________________________________________title: ______________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _______________ postal code: ___________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453.
please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required

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